The RequirementOne of the requirements in the ECE department at the University of Florida for all PhD students is to 'supervise teach' two undergraduate courses. The requirements of supervised teaching are loosely defined. Generally it is up to the student to do as much or as little as they would like. Some students will simply grade homework, others will take on more supervisory roles like serving as a substitute teacher when the lecturer is absent. I have had interest in teaching one day, so I took this an opportunity to gain experience and build on my teaching skills. In Spring of 2017, I was a supervised teacher in a Digital and Computer Architecture class. I was very excited about this, and it went over very well. I had taken a Computer Organization course in college, but it was taught from the perspective of a computer scientist. In that course we covered the standard material in the Patterson and Hennessy book "Computer Organization and Design" and tested the performance of the hardware under varying software conditions, but we never dove deep into the architecture at the hardware level. It was a good class, but I now had the engineering background to take the ideas from the book and give them meaning by doing hands on projects to design hardware to reproduce the architecture. In Fall of 2018, I was a supervised teacher in undergraduate Electromagnetic Fields, but I will discuss that in another post! DutiesAs a supervised teacher in Digital Computer Architecture, I performed the following duties:
Lab ComponentThe final goal of the lab portion of this course was to build a pipelined MIPS processor with some simple hazard detection and avoidance. Students entering this course have seen logic gates and memory units in a digital logic course and have expanded on those ideas in a digital design course where they should have built a single-cycle MIPS processor using VHDL. In this class we wanted to build further on these ideas by introducing, or at least digging deeper into, the notion of a datapath, pipeline, and data forwarding. We also wanted the students to gain more industry transferable skills, so we require the project be written in Verilog. The TA and I worked closely to update the past lab assignments to insert clarity where needed and reflect changes regarding specifics of Verilog programming syntax. We built up slowly to the multi-cycle processor, here are the labs we used to get there:
Class LecturesI led a series of lectures over the course of three days introducing the students to virtual memory. This topics follows the introduction of the cache hierarchy and covers some of the practical challenges of working with limited hardware resources. My lectures closely followed the material presented in the textbook, but I made a point to connect the material back to the problems we face when working with real computers and the FPGA we use in lab. I also add material covering the OS perspective as the boundary between hardware and software begins to fade in virtual memory.
One method I use in class is to introduce a snippet of content, then ask a question that extends this concept. I wait for students to respond and explain the solution fully before proceeding. These are not meant to be challenging, just to affirm a simple understanding of the broader concepts and to keep lecture interesting. This is something I learned from watching online video lectures where the videos are no more than 5 minutes long and are frequently followed by thoughtful, but simple, practice problems. This course is especially amenable to this type of lecture as the in-class component can be admittedly be dull, especially compared to the lab part, but is important to cover for a holistic understanding of the architecture. Like many computer-related classes, it can be difficult to use a board, which is my preference. In the interest of time (in class), I created a rather detailed set of slides that incrementally added small details rather than presenting all the information at once, more like what you would get if you were to draw it out by hand. The student feedback was very positive in this regard and I think it was well worth the effort on my part. On the third day of lecture, I finished early and we solved an in-class problem. I divided the class into groups of 3 and let them work through the problems as I walked around taking questions. In the remaining minutes of class, we went over the solutions on the board. I did not know how the students would react, but I had the impression that they liked getting more practice solving the problems. In the future, I would do something like this again.
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I am really looking forward to sharing material to this section of my website. I already have a list of things that you can expect to see. I anticipate showcasing select projects from my academic classes, projects I have designed as an instructor, course material I have created, and perhaps some work from my lab at UF.
Here is a start of what is to come:
There's bound to be much more, but for now I am sure this small list will keep me busy. I am contemplating posting my solutions to select book problems but am not sold on the idea yet. One project I have been dreaming up for a while is a macro-processor. That's right. Rather than making my hardware as small as possible, I want to make a processor as big as possible. I expect to have LEDs on all inputs and outputs of my logic gates so that I can trace the execution of the code in a tangible way. Maybe this one is silly, but I think it is neat! |
AcademicsHere I will share material relating to my work in the classroom, both as a student and instructor. Archives
July 2020
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